1. Field of the Invention
The present invention generally relates to debugging systems and debugging circuits, and more particularly to a debugging system and a debugging circuit for supporting debugging of an information processing apparatus, that are built into a microcontroller or the like. The present invention also relates to such an information processing apparatus that is a debugging target.
2. Description of the Related Art
In apparatuses including an information processing apparatus (hereinafter referred to as a CPU) that is typified by a microcontroller or the like, a debugging system is used in general when developing a program for operating the CPU. The debugging system supports the debugging, by displaying various operation information of the program that is to be developed, and providing a program developer with particular operating functions with respect to the program that is to be developed.
FIG. 1 is a system block diagram showing an example of a conventional debugging system. In FIG. 1, a 1-chip microcontroller 1 that is the target of the debugging, is connected to a host computer 3 via an external debugging apparatus 2. The microcontroller 1 has a CPU 11, a debugging circuit 12, a storage unit 31 and peripheral functions 14 and 15 that are connected via a bus 16. The microcontroller 1 is connected to the external debugging apparatus 2 via dedicated debugging pins 17.
The debugging system is formed by the debugging circuit 12 that is built into the microcontroller 1 and carries out various monitoring of the CPU 11, the external debugging apparatus 2 that carries out various debugging processes externally to the microcontroller 1, and the host computer 3 that executes a debugger software 10. The debugging circuit 12 and the external debugging apparatus 2 are connected via dedicated signal lines, and the external debugging apparatus 2 and the host computer 3 are connected via dedicated signal lines.
The trace functions are one of the main functions of the debugging system. The trace functions include an instruction trace function for obtaining execution log information of the instruction, and a data trace function for obtaining execution log information of the data access. It is extremely useful to obtain the log information (trace information) of the various operations of the CPU 11 in the debugging stage by these trace functions.
The amount of the trace information increases proportionally to the time required to acquire the trace information. In order to store a large amount of trace information in the debugging circuit 12 within the microcontroller 1, a storage unit having a large storage capacity is required within the debugging circuit 12, and both the chip area and the cost of the microcontroller 1 increase. For this reason, in general, a technique is used in which the debugging circuit 12 outputs the trace information to the external debugging apparatus 2, and the trace information is stored in the external debugging apparatus 2. This technique is used because there are no demands to form the external debugging apparatus 2 as a 1-chip device, and it is more advantageous from the point of view of the cost and the functions to provide the required storage unit in the external debugging apparatus 2 than to provide the storage unit having the large storage capacity in the debugging circuit 12 within the microcontroller 1.
FIG. 2 is a system block diagram showing structures of the debugging circuit 12 and the external debugging apparatus 2. The debugging circuit 12 has a trace apparatus 19. On the other hand, the external debugging apparatus 2 has a write control part 21, a trace data recording part 22, and a read control part 23. In the data trace function of the debugging system, when tracing the operation of the CPU 11 that is the debugging target, the trace apparatus 19 within the debugging circuit 12 monitors the data access of the CPU 11. When the trace apparatus 19 detects the access of the tracing target, the trace information is generated from the access type (read, write, size, etc.), the access address and the access data. Of the data accesses of the CPU 11 monitored by the debugging circuit 12, the stack access using the stack pointer (SP) and the data access excluding the stack access (hereinafter referred to as “a normal data access”) are not distinguished from each other. For example, the stack access is for a PUSH instruction, a POP instruction, an EIT (Exception, Interrupt and Trap), RETI instruction, a stack pointer relative access instruction or the like. Hence, the debugging circuit 12 treats both the stack access and the normal data access as the same trace information. In addition, the external debugging apparatus 2 which receives the trace information also treats the stack access and the normal data access as the same trace information.
After generating the trace information, the debugging circuit 12 outputs the trace information to the external debugging apparatus 2 via the dedicated debugging pins 17. In general, the dedicated debugging pins 17 are not used at times other than the debugging. For this reason, from the point of view of reducing the cost, it is desirable to realize the dedicated debugging pins 17, that are not used at time other than the debugging, by a smallest possible number of pins. In addition, it is desirable to compress the information output via the dedicated debugging pins 17, so as to output a maximum amount of information by a small number of pins and a limited bandwidth.
FIG. 3 is a diagram for explaining the data trace function. As shown in FIG. 3, when the debugger software 10 makes a data trace set instruction, the external debugging apparatus 2 initializes the write control part 21, and the debugging circuit 12 sets the data trace. In addition, when the debugger software 10 makes a trace start instruction with respect to the debugging target program, the CPU 11 starts execution of the debugging target program. The CPU 11 executes the debugging target program, the debugging circuit 12 generates the trace data, and the external debugging apparatus 2 records the trace data by the trace data recording part 22. The CPU 11 interrupts the execution of the debugging target program when a condition for interrupting execution of the debugging target program is satisfied, and the debugger software 10 detects the trace interruption of the debugging target program.
The debugger software 10 makes a trace data amount notifying instruction, and the external debugging apparatus 2 makes a trace data amount notification. The debugger software 10 makes a trace data read instruction, and the external debugging apparatus 2 reads and sends the trace data. Thereafter, the debugger software 10 receives the trace data, moves the received trace data in a work area, analyzes the received trace data, creates a trace list, and displays the trace result.
FIG. 4 is a diagram for explaining extraction of the stack access and the normal data access. FIG. 4 shows, time-sequentially, the data trace information that is output to the external debugging apparatus 2 via the dedicated debugging pins 17. In FIG. 4, shaded rectangular marks indicate the trace data of the stack access, and white rectangular marks indicate the trace data of the normal data access.
FIG. 5 is a diagram for explaining analysis and separation of the trace list of the data trace. In FIG. 5, the trace list shown on the left side is separated into a trace list of the normal data access and a trace list of the stack access that are shown on the right side, by an analyzing part 10A and a separating part 10B of the debugger software 10.
The conventional systems have the following first and second problems described hereunder.
The first problem is caused by the data trace that does not distinguish the stack access and the normal data access.
According to the conventional data trace, the debugging system does not distinguish the stack access and the normal data access from each other. Hence, the debugging circuit 12 treats the stack access and the normal data access as the same trace information, and outputs all of the trace information, including the stack access and the normal data access, via the dedicated debugging pins 17. For this reason, the external debugging apparatus 2 stores all of the trace information, including the stack access and the normal data access, in a storage unit (not shown). The debugger software 10 running on the host computer 3 creates a data access execution log list (trace list) based on the trace information that is stored in the external debugging apparatus 2. In the trace list that is created, the stack access and the normal data access are not distinguished from each other. Consequently, if only the stack access is to be traced or, only the normal data access is to be traced, the debugger software 10 running on the host computer 3 must carry out the processes of analyzing the trace list, and separating the trace list into a trace list of the stack access and a trace list of the normal data access.
For example, if only one of the stack access and the normal data access is to be traced, of the trace data output from the dedicated debugging pins 17, the trace data other than those of the trace target are finally discarded. For this reason, the trace data output from the dedicated debugging pins 17 include unnecessary trace data, thereby causing the limited bandwidth of the dedicated debugging pins 17 and the storage capacity of the storage unit that stores the trace data within the external debugging apparatus 2 to be unnecessarily large. Furthermore, in the process of separating the stack access and the normal data access, the resources such as the external debugging apparatus 2 and the host computer 3 are utilized, thereby increasing the load on the resources.
The second problem concerns the compression of the data trace information by positively utilizing the characteristics of the stack access.
As described above with respect to the first problem, the conventional data trace does not distinguish the stack access and the normal data access from each other. Hence, of the trace information of the data trace, the information of all of the bits of the address is compressed using a compression technique. In other words, the same address compression technique is used for the stack access and the normal data access. As a result, the compression rate of the stack access is the same as that of the normal data access. The compression technique based on the address information of all of the bits is proposed in Japanese Laid-Open Patent Applications No. 2004-178591 and No. 2004-38981, for example.
On the other hand, compared to the normal data access, the characteristics of the stack access are such that the address that is accessed has locality and continuity. A description will now be given of these characteristics of the stack access. FIGS. 6 through 8 are diagrams for explaining the stack access of a 32-bit CPU. FIG. 6 shows a PUSH access which pushes a general-purpose register R0, FIG. 7 shows a POP access which pops to the general-purpose register R0, and FIG. 8 shows a stack pointer relative access which writes to the general-purpose register R0 with an offset of +0x8 with respect to the value of the stack pointer.
Generally, the stack access includes the PUSH access to the stack, and the POP access from the stack. Particular examples of the PUSH access include CPU register save accesses at the time of the PUSH instruction and the EIT (Exception, Interrupt and Trap). When such a PUSH access is executed, the CPU decrements the stack pointer (SP) according to the data width for which the stack access is made, and thereafter makes a write access to the address indicated by the SP, as shown in FIG. 6. Particular examples of the POP access include CPU register restore accesses at the time of the POP instruction and the RETI instruction (interrupt return instruction). When such a POP access is executed, the CPU makes a read access from the address indicated by the SP, and thereafter increments the SP depending on the data width for which the stack access is made. Generally, the data widths of the PUSH access and the POP access are fixed, and the values with which the SP is decremented and incremented are fixed. Hence, in the case of the PUSH access or the POP access, the SP is incremented or decremented, and the address of the stack access has locality and continuity.
Although dependent upon the instruction set of the CPU, the stack access includes, in addition to the POP access and the PUSH access described above, an access using the SP. For example, there is the stack pointer relative access instruction that makes the stack pointer relative access (hereinafter referred to as an SP relative access). According to the SP relative access instruction, the CPU makes a read access or a write access to the address represented relatively from the SP using an offset value from the value of the SP included in the operand of the instruction. The address of the SP relative access has no continuity, but has locality since the access is made within the offset range from the SP.
It may be regarded extremely useful to compress the address portion of the trace information of the stack access by utilizing these characteristics. However, in the data access of the CPU monitored by the debugging circuit, the stack access and the normal data access are not distinguished from each other, and it is impossible to easily carry out a compression which utilizes the characteristics of the stack access.